It is known that, in semiconductor devices with vertical current flow (for example, bipolar transistors and field-effect transistors, IGBTs, Schottky diodes, and junction diodes), the maximum current in the conduction state is limited by the so-called active-state resistance (or ON resistance) present between the conduction terminals.
The ON resistance, which obviously is ideally minimized, is determined by the sum of various contributions, associated with the different structures that form the device. FIG. 1 schematically shows a succession of layers normally present in a vertical current flow device/encapsulated in a package 2. The encapsulated device/comprises a semiconductor die 3, coupled to a first electrode 4 and a second electrode 5 of the package 2 (herein shown only in part). The die 3 includes a substrate 6, which functions as support and as connection layer for active structures 7, not illustrated in detail (for example, source and channel regions of a MOS transistor). On a front side 3a of the die 3, the active structures 7 are provided with metal electrodes 8, coupled to the first electrode 4 of the package by means of wires or jumpers 9. A rear side 3b of the die 3, defined by a face of the substrate 6, is coated with a rear-metallization layer 10 and fixed to the second electrode 5 of the package by means of a conductive bonding layer 11.
The ON resistance is determined in part by the package (electrodes 4, 5, wires and/or jumpers 9, contacts), in part by the active structures 7 and in part by parasitic resistances of the substrate 6, of the rear-metallization layer 10, of the bonding layer 11 and of the corresponding interfaces. The development of innovative constructional solutions has enabled in recent times a substantial reduction in the resistance of the active structures 7. In the same way, the pressing need of reducing power consumption and of miniaturizing the components to be able to incorporate them in increasingly sophisticated portable apparatuses has accelerated the development also of the packages both from the standpoint of the overall dimensions and from the electrical standpoint, reducing further the ON resistance.
Especially in some relatively low-voltage (20-30 volts) applications, increasing importance is associated with the contributions of the parasitic substrate resistance, of the contact interface with the rear-metallization layer 10 and, to a lesser extent, of the resistance of the rear-metallization layer 10 itself and of the bonding layer 11. On the one hand, then, it would be desirable to decrease the contribution of the structures listed above to the ON resistance. On the other hand, the parasitic substrate resistance, which has a determining weight, depends basically upon the thickness of the substrate 5, which cannot be reduced beyond a certain limit (approximately 100 μm). Otherwise, in fact, the substrate 5 would lose its mechanical function of support both during machining of the semiconductor wafers and after cutting and separation of the devices produced, and the risk of collapse of the structures would be too high.